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general description the max9400/max9402/max9403/max9405 are extremely fast, low-skew quad lvecl/ecl or lvpecl/ pecl buffer/receivers designed for high-speed data and clock driver applications. these devices feature an ultra-low propagation delay of 335ps and channel-to- channel skew of 16ps in asynchronous mode with 86ma supply current. the four channels can be operated synchronously with an external clock, or in asynchronous mode determined by the state of the sel input. an enable input provides the ability to force all the outputs to a differential low state. a variety of input and output terminations are offered for maximum design flexibility. the max9400 has open inputs and open emitter outputs. the max9402 has open inputs and 50 ? series outputs. the max9403 has 100 ? differential input impedance and open emitter outputs. the max9405 has 100 ? differential input impedance and 50 ? series outputs. these devices operate with a supply voltage of (v cc - v ee ) = 2.375v to 5.5v, and are specified for operation from -40? to +85?. these devices are offered in space-saving 32-pin 5mm ? 5mm tqfp and 32-lead 5mm ? 5mm qfn packages. applications data and clock driver and buffer central office backplane clock distribution dslam backplane base station ate features 400mv differential output at 3.0ghz data rate 335ps propagation delay in asynchronous mode 8ps channel-to-channel skew in synchronous mode integrated 50 ? outputs (max9402/max9405) integrated 100 ? inputs (max9403/max9405) synchronous/asynchronous operation max9400/max9402/max9403/max9405 quad differential lvecl/lvpecl buffer/receivers ________________________________________________________________ maxim integrated products 1 ordering information max9400 max9402 max9403 max9405 tqfp (5mm x 5mm) top view 32 28 29 30 31 25 26 27 in0 v cc out0 out0 in0 v ee in1 in1 10 13 15 14 16 11 12 9 in3 v cc out3 in2 v ee 17 18 19 20 21 22 23 out1 24 v cc out1 v ee v ee out2 out2 v cc 2 3 4 5 6 7 8 v cc en clk sel 1 v cc sel clk en in3 out3 in2 pin configurations 19-2223; rev 1; 1/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. functional diagram appears at end of data sheet. part temp range pin- package data input output max9400 ehj -40 c to +85 c 32 tqfp open open max9400egj* -40 c to +85 c 32 qfn open open max9402 ehj -40 c to +85 c 32 tqfp open 50 ? max9402egj* -40 c to +85 c 32 qfn open 50 ? max9403 ehj -40 c to +85 c 32 tqfp 100 ? open MAX9403EGJ* -40 c to +85 c 32 qfn 100 ? open max9405 ehj -40 c to +85 c 32 tqfp 100 ? 50 ? max9405egj* -40 c to +85 c 32 qfn 100 ? 50 ? pin configurations continued at end of data sheet. * future product?ontact factory for availability.
max9400/max9402/max9403/max9405 quad differential lvecl/lvpecl buffer/receivers 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc - v ee = 2.375v to 5.5v, max9400/max9403 outputs terminated with 50 ? 1% to v cc - 2.0v. typical values are at v cc - v ee = 3.3v, v ihd = v cc - 0.9v, v ild = v cc - 1.7v, t a = +25 c, unless otherwise noted.) (notes 1, 2, and 3) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to v ee ................................................................-0.3v to +6v inputs to v ee ...............................................-0.3v to (v cc + 0.3v) differential input voltage .......................................................3v continuous output current .................................................50ma surge output current........................................................100ma continuous power dissipation (t a = +70 c) 32-pin 5mm x 5mm tqfp (derate 9.5mw/ c above +70 c) .................................761mw 32-lead 5mm x 5mm qfn (derate 21.3mw/ c above +70 c) ...................................1.7w junction-to-ambient thermal resistance in still air 32-pin 5mm x 5mm tqfp ........................................+105 c/w 32-lead 5mm x 5mm qfn ........................................+47 c/w junction-to-ambient thermal resistance with 500lfpm airflow 32-pin 5mm x 5mm tqfp .........................................+73 c/w junction-to-case thermal resistance 32-pin 5mm x 5mm tqfp .........................................+25 c/w 32-lead 5mm x 5mm qfn .........................................+2 c/w operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c esd protection human body model (inputs and outputs) ........................2kv soldering temperature (10s) ...........................................+300 c parameter symbol conditions min typ max units inputs (in_, in_ , clk, clk , en, en , sel, sel ) differential input high voltage v ihd figure 1 v ee + 1.4 v cc v differential input low voltage v ild figure 1 v ee v cc - 0.2 v v cc - v ee < +3.0v 0.2 v cc - v ee differential input voltage v id figure 1 v cc - v ee +3.0v 0.2 3.0 v max9400/ max9402 en, en , sel, sel , in_, i n_ , clk, or clk = v ihd or v ild -10 25 input current i ih , i il max9403/ max9405 en, en , sel, sel , clk, or clk = v ihd or v ild -10 25 a differential input resistance r in max9403/max9405 86 114 ? outputs (out_, out_ ) differential output voltage v oh - v ol figure 1 600 660 mv output common-mode voltage v ocm figure 1 v cc - 1.5 v cc - 1.25 v cc - 1.1 v internal current source i sink max9402/max9405, figure 2 6.5 8.3 10 ma output impedance r out max9402/max9405, figure 2 40 50 60 ? power supply max9402/max9405 150 180 supply current i ee max9400/max9403 86 118 ma
max9400/max9402/max9403/max9405 quad differential lvecl/lvpecl buffer/receivers _______________________________________________________________________________________ 3 ac electrical characteristics (v cc - v ee = 2.375v to 5.5v, outputs terminated with 50 ? 1% to v cc - 2.0v, enabled, clk = 3.2ghz, f in = 1.6ghz, input transition time = 125ps (20% to 80%), v ihd = v ee + 1.2v to v cc , v ild = v ee to v cc - 0.2v, v ihd - v ild = 0.2v to smaller of |v cc - v ee | or 3v, unless otherwise noted. typical values are at v cc - v ee = 3.3v, v ihd = v cc - 0.9v, v ild = v cc 1.7v, t a = +25 c, unless otherwise noted.) (notes 1, 4) parameter symbol conditions min typ max units max9400/max9403 237 335 437 in-to-out differential propagation delay t plh1 t phl1 max9402/max9405 sel = high, figure 3 237 335 437 ps max9400/max9403 397 475 597 clk-to-out differential propagation delay t plh2 t phl2 max9402/max9405 sel = low, figure 4 397 475 597 ps in-to-out channel-to-channel skew (note 5) t skd1 sel = high 16 80 ps clk-to-out channel-to- channel skew (note 5) t skd2 sel = low 8 55 ps maximum clock frequency f clk ( max ) v oh - v ol 500mv, sel = low 3.0 ghz maximum data frequency f in ( max ) v oh - v ol 400mv, sel = high 2 ghz sel = low, f clk = 3.0ghz clock, f in = 1.5ghz 0.64 1.3 added random jitter (note 6) t rj sel = high, f in = 2ghz 0.74 1.5 ps ( rms ) sel = low, f clk = 3.0ghz, in_ = 3.0gbps 2 23 - 1 prbs pattern 17 30 added deterministic jitter (note 6) t dj sel = high, in = 2.0gbps 2 23 - 1 prbs pattern 40 55 ps ( p-p ) in-to-clk setup time t s figure 4 80 ps clk-to-in hold time t h figure 4 80 ps output rise time t r figure 3 80 120 ps output fall time t f figure 3 80 120 ps propagation delay temperature coefficient ? t pd / ? t 0.2 1 ps/ c note 1: measurements are made with the device in thermal equilibrium. note 2: current into a pin is defined as positive. current out of a pin is defined as negative. note 3: dc parameters are production tested at +25 c. dc limits are guaranteed by design and characterization over the full oper- ating temperature range. note 4: guaranteed by design and characterization. limits are set to 6 sigma. note 5: measured between outputs of the same part at the signal crossing points for a same-edge transition. note 6: device jitter added to the input signal.
max9400/max9402/max9403/max9405 quad differential lvecl/lvpecl buffer/receivers 4 _______________________________________________________________________________________ typical operating characteristics (v cc - v ee = 3.3v, max9400, outputs terminated with 50 ? 1% to v cc - 2.0v, enabled, sel = high, clk = 2.0ghz, f in = 1.0ghz, input transition time = 125ps (20% to 80%), v ihd = v cc - 1.0v, v ild = v cc - 1.5v, t a = +25 c, unless otherwise noted.) 70 75 85 80 90 95 -40 10 -15 35 60 85 supply current (i ee ) vs. temperature max9400 toc01 temperature ( c) supply current (ma) 0 200 600 400 800 1000 0 1000 500 1500 2000 2500 3000 3500 output amplitude (v oh - v ol ) vs. in_ frequency max9400 toc02 in_ frequency (mhz) output amplitude (mv) 100 90 80 70 60 -40 10 -15 35 60 85 output rise/fall vs. temperature max9400 toc03 temperature ( c) output rise/fall time (ps) t r t f 325 335 330 345 340 350 355 -40 85 in-to-out propagation delay vs. temperature max9400 toc04 temperature ( c) propagation delay (ps) 10 -15 35 60 t plh t phl 520 500 480 460 440 -40 10 -15 35 60 85 clk-to-out propagation delay vs. temperature max9400 toc05 temperature ( c) propagation delay (ps) t plh2 t phl2
max9400/max9402/max9403/max9405 quad differential lvecl/lvpecl buffer/receivers _______________________________________________________________________________________ 5 pin description pin name function 1, 8,11, 17, 24, 30 v cc positive supply voltage. bypass v cc to v ee with 0.1f and 0.01f ceramic capacitors. place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2 sel noninverting differential select input. setting sel = high and sel = low (differential high) enables all four channels to operate asynchronously. setting sel = low and sel = high (differential low) enables all four channels to operate in synchronous mode. 3 sel inverting differential select input 4 clk noninverting differential clock input 5 clk inverting differential clock input. a rising edge on clk (and falling on clk ) transfers data from the inputs to the outputs when sel = low. 6en noninverting differential output enable input. setting en = high and en = low (differential high) enables the outputs. setting en = low and en = high (differential low) drives outputs low. 7 en inverting differential output enable input 9 in3 noninverting differential input 3 10 in3 inverting differential input 3 12 out3 inverting differential output 3 13 out3 noninverting differential output 3 14, 20, 21, 27 v ee negative supply voltage 15 in2 noninverting differential input 2 16 in2 inverting differential input 2 18 out2 inverting differential output 2 19 out2 noninverting differential output 2 22 out1 noninverting differential output 1 23 out1 inverting differential output 1 25 in1 inverting differential input 1 26 in1 noninverting differential input 1 28 out0 noninverting differential output 0 29 out0 inverting differential output 0 31 in0 inverting differential input 0 32 in0 noninverting differential input 0 ep exposed paddle (max940_egj only). connected to v ee internally. see package dimensions.
max9400/max9402/max9403/max9405 detailed description the max9400/max9402/max9403/max9405 are extremely fast, low-skew quad lvecl/ecl or lvpecl/ pecl buffer/receivers designed for high-speed data and clock driver applications. the devices feature an ultra-low propagation delay of 335ps and channel-to- channel skew of 16ps in asynchronous mode with an 86ma supply current. the four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the sel input. an enable input provides the ability to force all the outputs to a differential low state. a variety of input and output terminations are offered for maximum design flexibility. the max9400 has open inputs and open-emitter outputs. the max9402 has open inputs and 50 ? series outputs. the max9403 has 100 ? differential input impedance and open-emitter outputs. the max9405 has 100 ? differential input impedance and 50 ? series outputs. supply voltage the max9400/max9402/max9403/max9405 are de- signed for operation with a single supply. using a single negative supply of v ee = -2.375v to -5.5v (v cc = ground) yields lvecl/ecl-compatible input and output levels. using a single positive supply of v cc = 2.375v to 5.5v (v ee = ground) yields lvpecl/pecl input and output levels. data inputs the max9400/max9402 have open inputs and require external termination. the max9403/max9405 have inte- grated 100 ? differential input termination resistors from in_ to in_, reducing external component count. outputs the max9402/max9405 have internal 50 ? series out- put termination resistors and 8ma internal pulldown current sources. using integrated resistors reduces external component count. the max9400/max9403 have open-emitter outputs. an external termination is required. see the output termination section. enable setting en = high and en = low enables the device. setting en = low and en = high forces the outputs to a differential low, and all changes on clk, sel, and in_ are ignored. asynchronous operation setting sel = high and sel = low enables the four channels to operate independently as buffer/receivers. the clk signal is ignored in this mode. in asynchro- nous mode, the clk signal should be set to either a logic low or high state to minimize noise coupling. synchronous operation setting sel = low and sel = high enables all four channels to operate in synchronous mode. in this mode, buffered inputs are clocked into flip-flops simul- taneously on the rising edge of the differential clock input (clk and clk ). differential signal input limit the maximum signal magnitude of the differential inputs is v cc - v ee or 3v, whichever is less. applications information input bias unused inputs should be biased or driven as shown in figure 5. this avoids noise coupling that might cause toggling at the unused outputs. output termination terminate open-emitter outputs (max9400/max9403) through 50 ? to v cc - 2v or use an equivalent thevenin termination. terminate both outputs and use identical termination on each for the lowest output-to-output skew. when a single-ended signal is taken from a dif- ferential output, terminate both outputs. for example, if out_ is used as a single-ended output, terminate both out_ and out_ . ensure that the output currents do not exceed the cur- rent limits as specified in the absolute maximum ratings table. under all operating conditions, the device s total thermal limits should be observed. power-supply bypassing adequate power-supply bypassing is necessary to maximize the performance and noise immunity. bypass v cc to v ee with high-frequency surface-mount ceramic 0.1f and 0.01f capacitors as close to the device as possible with the 0.01f capacitor closest to the device pins. use multiple bypass vias for connection to mini- mize inductance. circuit board traces input and output trace characteristics affect the perfor- mance of the max9400/max9402/max9403/max9405. connect each of the inputs and outputs to a 50 ? char- acteristic impedance trace. avoid discontinuities in dif- ferential impedance and maximize common-mode noise immunity by maintaining the distance between differential traces and avoid sharp corners. minimize the number of vias to prevent impedance discontinu- ities. reduce reflections by maintaining the 50 ? char- quad differential lvecl/lvpecl buffer/receivers 6 _______________________________________________________________________________________
acteristic impedance through connectors and across cables. minimize skew by matching the electrical length of the traces. chip information transistor count: 713 process: bipolar max9400/max9402/max9403/max9405 quad differential lvecl/lvpecl buffer/receivers _______________________________________________________________________________________ 7 v cc v id v id = 0v v ihd (max) v cc v ee v ild (max) v oh - v ol v ocm v oh v ol v ee v id v id = 0v v ihd (min) v ild (min) input voltage definition output voltage definition figure 1. input and output voltage definitions in_ in_ in_ in_ v cc out_ out_ v cc v ee out_ out_ 50 ? 50 ? 8ma 8ma max9420/max9421 max9422/max9423 max9421/max9423 max9420/max9422 100k ? figure 2. input and output configurations
max9400/max9402/max9403/max9405 quad differential lvecl/lvpecl buffer/receivers 8 _______________________________________________________________________________________ t plh1 t phl1 v oh - v ol v ihd - v ild v oh - v ol v oh - v ol t r t f 80% 20% 20% 80% differential output waveform in_ in_ out_ out_ out_ - out_ sel = high en = high figure 3. in-to-out propagation delay and transition timing diagram v ihd - v ild v ihd - v ild v ihd - v ild clk clk in_ in_ out_ out_ t h t s t h t plh2 t phl2 sel = low en = high figure 4. clk-to-out propagation delay timing diagram
max9400/max9402/max9403/max9405 quad differential lvecl/lvpecl buffer/receivers _______________________________________________________________________________________ 9 in_ in_ 100 ? 1k ? v cc v ee 1/4 max9400/max9402 out_ out_ in_ in_ 1k ? v cc v ee 1/4 max9403/max9405 out_ out_ 100 ? figure 5. input bias circuits for unused inputs 32 31 30 29 28 27 26 in0 in0 v cc out0 out0 v ee in1 25 in1 9 10 11 12 13 14 15 in3 in3 v cc out3 out3 v ee in2 16 in2 17 18 19 20 21 22 23 v cc *exposed paddle and corner pins are connected to v ee . out2 out2 v ee v ee out1 out1 8 7 6 5 4 3 2 v cc en en clk clk sel sel max9400 max9402 max9403 max9405 qfn-ep* 1 v cc 24 v cc top view *exposed paddle * * * * pin configurations (continued)
max9400/max9402/max9403/max9405 quad differential lvecl/lvpecl buffer/receivers 10 ______________________________________________________________________________________ functional diagram dq ck d q ck 1 0 in0 in0 out0 out0 dq ck d q ck 1 0 in1 in1 out1 out1 dq ck d q ck 1 0 in2 in2 out2 out2 dq ck d q ck 1 0 in3 in3 clk clk sel sel en en out3 out3
max9400/max9402/max9403/max9405 quad differential lvecl/lvpecl buffer/receivers ______________________________________________________________________________________ 11 package information 32l tqfp, 5x5x01.0.eps
max9400/max9402/max9403/max9405 quad differential lvecl/lvpecl buffer/receivers 12 ______________________________________________________________________________________ package information (continued)
max9400/max9402/max9403/max9405 quad differential lvecl/lvpecl buffer/receivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued)

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